256Mb: x32 Mobile SDRAM
Features
Mobile SDRAM
MT48LC8M32LF, MT48V8M32LF, MT48H8M32LF - 2 Meg x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/dram/mobile
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Options
• VDD/VDDQ
• 3.3V/3.3V
• 2.5V/2.5V
• 1.8V/1.8V
• Configurations
• 8 Meg x 32 (2 Meg x 32 x 4 banks)
• Package/Ballout
• 90-ball VFBGA (8mm x 13mm)
(Standard)
• 90-ball VFBGA (8mm x 13mm)
(Lead-free)
• Timing (Cycle Time)
• 7.5ns @ CL = 3 (133 MHz)
• 7.5ns @ CL = 2 (104 MHz)
• 8ns @ CL = 3 (125 MHz)
• 8ns @ CL = 2 (104 Mhz)
• 10ns @ CL = 3 (100 MHz)
• 10ns @ CL = 2 (83 Mhz)
• Operating Temperature Range
• Commercial (0° to +70°C)
• Industrial (-40°C to +85°C)
Low voltage power supply
Partial array self refresh power-saving mode
Temperature Compensated Self Refresh (TCSR)
Deep power-down mode
Programmable output drive strength
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto
precharge, and auto refresh modes
Self-refresh mode; standard and low power
64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Commercial and industrial temperature ranges
Supports CAS latency of 1, 2, 3
Table 1: Addressing
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_1.fm - Rev. G 6/05
LC
V
H
8M32
F5
B5
-75
-75
-8
-8
-10
-10
None
IT
Table 2: Key Timing Parameters
CL = CAS (READ) latency
8 Meg x 32
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
Marking
2 Meg x 32 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
1
Access Time
Speed
Grade
Clock
Frequency
CL = 2
CL = 3
Setup
Time
Hold
Time
-75
-8
-10
-75
-8
-10
133 MHz
125 MHz
100 MHz
133 MHz
104 MHz
83 MHz
–
–
–
7ns
8ns
8ns
6ns
7ns
7ns
–
–
-
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
1ns
1ns
1ns
1ns
1ns
1ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: x32 Mobile SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FBGA Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32TOC.fm - Rev. G 6/05
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
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Figure 10:
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Figure 32:
Figure 33:
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Figure 36:
Figure 37:
Figure 38:
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Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Figure 52:
Figure 53:
Functional Block Diagram 8 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
90-Ball VFBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Low Power Extended Mode Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ to WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Typical Self Refresh Current vs. Temperature – 3.3V Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Typical Self Refresh Current vs. Temperature – 2.5V Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Typical Self Refresh Current vs. Temperature – 1.8V Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Initialize and Load Mode Register1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
READ – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Read – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Single Read – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Single Read – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Alternating Bank Read Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Read – Full-page Burst1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Read – DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Write – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Write – With Auto Precharge1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Single Write – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Single Write – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Alternating Bank Write Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Write – Full-page Burst1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Write – DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
90-Ball VFBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32LOF.fm - Rev. G 6/05
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Cross Reference For VFBGA Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Truth Table – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Truth Table – Current State Bank n, Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Truth Table – Current State Bank n, Command To Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
DC Electrical Characteristics and Operating Conditions (LC version) . . . . . . . . . . . . . . . . . . . . . . . . . .46
DC Electrical Characteristics and Operating Conditions (V version) . . . . . . . . . . . . . . . . . . . . . . . . . . .47
DC Electrical Characteristics and Operating Conditions (H version) . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .48
AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (LC version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (V version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
IDD Specifications and Conditions (H version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
IDD7 – Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
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256Mb SDRAM x32LOT.fm - Rev. G 6/05
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
FBGA Part Number System
Table 3: Cross Reference For VFBGA Device Marking
Part Number
VDD/VDDQ
Architecture
VFBGA
Production
Marking
MT48LC8M32LFF5-75
MT48LC8M32LFF5-8
MT48LC8M32LFF5-10
MT48LC8M32LFB5-75
MT48LC8M32LFB5-8
MT48LC8M32LFB5-10
MT48V8M32LFF5-75
MT48V8M32LFF5-8
MT48V8M32LFF5-10
MT48V8M32LFB5-75
MT48V8M32LFB5-8
MT48V8M32LFB5-10
MT48H8M32LFF5-75
MT48H8M32LFF5-8
MT48H8M32LFF5-10
MT48H8M32LFB5-75
MT48H8M32LFB5-8
MT48H8M32LFB5-10
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
2.5V/2.5V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
90-ball, 8 x 13mm
D9FMQ
D9CCH
D9CCK
D9FMX
D9CCW
D9CCZ
D9FMS
D9CCM
D9CCP
D9FMZ
D9CDC
D9CDF
D9FMV
D9CCR
D9CCT
D9FNB
D9CDJ
D9CDL
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see
the FBGA part marking decoder on Micron’s Web site, www.micron.com/decoder.
General Description
The Micron® 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32
bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high-
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256Mb SDRAM x32_2.fm - Rev. G 6/05
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
General Description
speed, fully random access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless high-speed, random-access
operation.
The 256Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V low-power memory
systems. An auto refresh mode is provided, along with a power-saving, deep powerdown mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle during a burst access.
Figure 1: Functional Block Diagram 8 Meg x 32 SDRAM
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 32)
4
DQM0,
DQM3
SENSE AMPLIFIERS
32
4096
14
ADDRESS
REGISTER
2
DATA
OUTPUT
REGISTER
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0-A11,
BA0, BA1
4
BANK
CONTROL
LOGIC
32
32
512
(x32)
DQ0DQ31
DATA
INPUT
REGISTER
COLUMN
DECODER
9
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256Mb SDRAM x32_2.fm - Rev. G 6/05
COLUMNADDRESS
COUNTER/
LATCH
9
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
Ball Assignment
Ball Assignment
Figure 2: 90-Ball VFBGA (Top View)
1
2
3
DQ26
DQ24
DQ28
4
5
6
7
8
9
VSS
VDD
DQ23
DQ21
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
NC
NC
DQ16
VSSQ
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
NC
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
DQ13
DQ15
VSS
VDD
DQ0
DQ2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
Ball Descriptions
Ball Descriptions
Table 4: Ball Descriptions
90-Ball VFBGA
Symbol
Type
Description
J1
CLK
Input
J2
CKE
Input
J8
CS#
Input
J9, K7, K8
RAS#,CAS#,
WE#
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank), DEEP POWER DOWN (all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. DQM0 corresponds to
DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16DQ23, and DQM3 corresponds to DQ24-DQ31. DQM0-3 are considered
same state when referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These balls also
provide the op-code during a LOAD MODE REGISTER command
Address Inputs: A0–A11 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A8;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
Data Input/Output: Data bus.
K9, K1, F8, F2
Input
DQM0-3
J7, H8
BA0, BA1
Input
G8, G9, F7, F3, G1, G2,
G3, H1, H2, J3, G7,H9
A0–A11
Input
R8, N7, R9, N8, P9, M8,
M7, L8, L2, M3, M2, P1,
N2, R1, N3, R2, E8, D7,
D8, B9, C8, A9, C7, A8,
A2, C3, A1, C2, B1, D2,
D3, E2
E3, E7, H3, H7, K2, K3
DQ0–DQ31
I/O
NC
–
B2, B7, C9, D9, E1, L1,
M9, N9, P2, P7
B3, B8, C1, D1, E9, L9,
M1, N1, P3, P8
A7, F9, L7, R7
A3, F1, L3, R3
VDDQ
Internally Not Connected: These could be left unconnected, but it is
recommended they be connected to Vss. H3 is a no connect for this part,
but may be used as A12 in future designs.
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD
VSS
Supply Core Power Supply.
Supply Ground.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
Functional Description
Functional Description
In general, the 256Mb SDRAMs (2 Meg x 32 x 4 banks) are quad-bank DRAMs that operate at 3.3V, 2.5V, and 1.8V and include a synchronous interface (all signals are registered
on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (A0–A8) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command
descriptions, and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once the power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock ball), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
Register Definition
Mode Register
In order to achieve low power consumption, there are two mode registers in the component: mode register and extended mode register. Extended mode register is illustrated in
Figure 5. The mode register is used to define the specific mode of operation of the
SDRAM. This definition includes the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as shown in Figure 3. The mode register is programmed via the LOAD MODE REGISTER command and will retain the
stored information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the write burst mode, and M10 and M11 should be set to
zero. M12 and M13 should be set to zero to prevent the extended mode register from
being programmed.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
Register Definition
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The fullpage burst is used in conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8.
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 4.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
Register Definition
Figure 3: Mode Register Definition
BA1 BA0
A9
A11 A10
A8
M13 M12 M11 M10 M9 M8
13
0
12
0
11
10
9
Reserved* WB
8
A7
A6
M7 M6
6
7
Op Mode
A5
A4
A3
M5
M4
5
4
CAS Latency
A2
M3
M2
3
M0
0
Mode Register (Mx)
Burst Length
Burst Length
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
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256Mb SDRAM x32_2.fm - Rev. G 6/05
Address Bus
A0
M1
1
2
BT
A1
CAS Latency
0
0
0
Reserved
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
11
All other states reserved
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©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
Register Definition
Table 5: Burst Definition Table
Order of Accesses Within a Burst
Burst Length Starting Column Address
2
4
8
Full Page (y)
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
n = A0-A11/9/8
(location
0-y)
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1,
Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
Notes: 1. For full-page accesses: y = 512.
2. For BL = 2, A1–A8 select the block-of-two burst; A0 selects the starting column within the
block.
3. For BL = 4, A2–A8 select the block-of-four burst; A0-A1 select the starting column within
the block.
4. For BL = 8, A3–A8 select the block-of-eight burst; A0-A2 select the starting column within
the block.
5. For a full-page burst, the full row is selected and A0–A8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7. For BL = 1, A0–A8 select the unique column to be accessed, and mode register bit M3 is
ignored.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one,
two, or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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256Mb: x32 Mobile SDRAM
Register Definition
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 4. Table 5 indicates the operating frequencies
at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and
WRITE bursts; when M9= 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
Low-Power Extended Mode Register Definition
The low-power extended mode register controls the functions beyond those controlled
by the mode register. These additional functions are special features of the mobile
device. They include temperature compensated self refresh (TCSR) control, partial array
self refresh (PASR), and output drive strength. Not programming the extended mode
register upon initialization will result in default settings for the low-power features. The
extended mode will default with the temperature sensor enabled, full drive strength, and
full array refresh.
The low-power extended mode register is programmed via the MODE REGISTER SET
command (BA1 = 1, BA0 = 0) and retains the stored information until it is programmed
again or the device loses power.
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Register Definition
Figure 4: CAS Latency
T0
T1
T2
READ
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 1
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
DON’T CARE
UNDEFINED
Table 6: CAS Latency
Allowable Operating Frequency (MHz)
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256Mb SDRAM x32_2.fm - Rev. G 6/05
Speed
CL = 1
CL = 2
CL = 3
-75
-8
-10
−
≤50
≤50
≤104
≤104
≤83.3
≤133
≤125
≤100
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Register Definition
Figure 5: Low Power Extended Mode Register Table
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E131 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
13 12 11 10
1
9
8
7
0 All must be set to "0"
Driver Strength
Full Strength2
E6
E5
0
0
0
1
1
0
Half Strength
RFU
1
1
RFU
6
5
DS
4
0
3
2
0
1
0
PASR
E4
E3
0
0 Must be set to "0"
Address Bus
Low Power
Extended Mode
Register (Ex)
E2
E1 E0 Self Refresh Coverage
0
0
0 Four Banks2
0
0
1 Two Banks (Bank 0,1)
0
1
0
1
0 One Bank (Bank 0)
1 RFU3
1
0
0 RFU
1
0
1 1/2 Bank (Bank 0)
1
1
0 1/4 Bank (Bank 0)
1
1
1 RFU
Notes: 1. E13 and E12 (BA1 and BA0) must be “1, 0” to select the extended mode register (vs. the
base mode register).
2. Default EMR values are full array for PASR, full drive strength.
3. RFU: reserved for future use.
4. E4 and E3 are “Don’t Care.”
The low-power extended mode register must be programmed with E7 through E11 set to
“0”. It must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating
either of these requirements results in unspecified operation. Once the values are
entered, the extended mode register settings will be retained even after exiting deep
power-down mode.
Temperature Compensated Self Refresh
Temperature compensated self refresh (TCSR) allows the controller to program the
refresh interval during self refresh mode, according to the case temperature of the
Mobile device. This allows great power savings during self refresh during most operating
temperature ranges. Only during extreme temperatures would the controller have to
select the maximum TCSR level. This would guarantee data during self refresh.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over
time. The refresh rate is dependent on temperature. At higher temperatures a capacitor
loses charge quicker than at lower temperatures, requiring the cells to be refreshed more
often. Historically, during self refresh, the refresh rate has been set to accommodate the
worst case, or highest temperature range expected.
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256Mb: x32 Mobile SDRAM
Register Definition
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher temperatures.
This SDRAM has an on-chip temperature sensor that automatically adjusts refresh rate
according to die temperature. The default setting for the TCSR is with the temperature
sensor enabled.
Partial Array Self Refresh
For further power savings during self refresh, the partial array self refresh (PASR) feature
allows the controller to select the amount of memory that will be refreshed during self
refresh. The refresh options are all banks (banks 0, 1, 2, and 3), two banks (banks 0 and
1), and one bank (bank 0). Also included in the refresh options are the half-bank and
quarter-bank partial array self refresh (bank 0). WRITE and READ commands occur to
any bank selected during standard operation, but only the selected banks in PASR will
be refreshed during self refresh. It is important to note that data in banks 2 and 3 will be
lost when the two bank option is used. Data will be lost in banks 1, 2, and 3 when the one
bank option is used.
Driver Strength
Bits E5 and E6 of the extended mode register can be used to select the driver strength of
the DQ outputs. This value should be set according to the application’s requirements.
Full drive strength was carried over from standard SDRAM and is suitable to drive higher
load systems.
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256Mb: x32 Mobile SDRAM
Commands
Commands
Table 7 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear following "Operation" on page 21; these tables provide current state/next state information.
Table 7: Truth Table – Commands and DQM Operation
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN
Name (Function)
CS#
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER DOWN
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
RAS# CAS# WE#
DQM
ADDR
DQs
Notes
H
L
L
L
L
L
X
H
L
H
H
H
X
H
H
L
L
H
X
H
H
H
L
L
X
X
X
L/H8
L/H8
X
X
X
Bank/Row
Bank/Col
Bank/Col
X
X
X
X
X
Valid
X
1
2
2
3, 4
L
L
L
L
H
L
L
H
X
X
Code
X
X
X
5
6, 7
L
X
X
L
X
X
L
X
X
L
X
X
X
L
H
Op-Code
X
X
X
Active
High-Z
8
9
9
Notes: 1. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
2. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which
bank is being read from or written to.
3. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER DOWN when CKE
is LOW.
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on the bus. However the DQs column reads a don’t care
state to illustrate that the BURST TERMINATE command can occur when there is no data
present.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
8. A0–A11 define the op-code written to the mode and extended mode register.
9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay). DQM0 controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23;
and DQM3 control DQ24–DQ31.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected and the DQ balls tri-state. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
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Commands
LOAD MODE REGISTER
The mode register is loaded via inputs A0, BA0, and BA1. (See "Mode Register" on page
9.) The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands
can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
The values of the load mode register and extended mode register will be retained even
when exiting deep power-down mode.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A11 selects the row. This row remains active (or open) for accesses
until a PRECHARGE command is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears on the DQs subject to the logic
level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH,
the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered
LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQs is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored,
and a write will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the precharge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE com-
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Commands
mand is automatically performed upon completion of the READ or WRITE burst, except
in the full-page burst mode, where auto precharge does not apply. Auto precharge is non
persistent in that it is either enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in "Operation" on
page 21.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in "Operation" on page 21.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is non persistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the PRECHARGE command, as shown in "Operation" on page 21.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 256Mb SDRAM requires
4,096 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO
REFRESH command every 15.625µs will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a
burst at the minimum cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain in self refresh mode for an
indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
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Commands
DEEP POWER-DOWN
DEEP POWER-DOWN is an operating mode to achieve maximum power reduction by
eliminating the power of the whole memory array of the devices. Array data will not be
retained once the device enters deep power-down mode. The settings in the mode and
extended mode register will be retained during deep power-down.
This mode is entered by having all banks idle then CS# and WE# held LOW with RAS#
and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is
exited by asserting CKE HIGH.
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Operation
Operation
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 5 on page 15).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 6 on page 21, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined
by tRRD.
Figure 6: Activating a Specific Row in a Specific Bank
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0-A11
BANK
ADDRESS
BA0, BA1
DON´T CARE
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Operation
Figure 7: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
T0
T1
T2
T3
CLK
tCK
tCK
COMMAND
ACTIVE
NOP
tCK
NOP
READ or
WRITE
tRCD (MIN)
DON’T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 8.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. Figure 9 shows general timing
for each possible CAS latency setting.
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Operation
Figure 8: READ Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0–A8
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0,BA1
DON’T CARE
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one.
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Operation
Figure 9: CAS Latency
T0
T1
T2
READ
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 1
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
DON’T CARE
UNDEFINED
This is shown in Figure 10 for CAS latencies of one, two, and three; data element n + 3 is
either the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM
uses a pipelined architecture and therefore does not require the 2n rule associated with
a prefetch architecture. A READ command can be initiated on any clock cycle following
a previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 10 on page 25, or each subsequent READ may be performed to a different bank.
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256Mb: x32 Mobile SDRAM
Operation
Figure 10: Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
READ
X = 0 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CL = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
READ
NOP
NOP
X = 2 cycles
ADDRESS
BANK,
COL b
BANK,
COL n
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CL = 3
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
Each READ command may be to either bank. DQM is LOW.
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256Mb: x32 Mobile SDRAM
Operation
Figure 11: Random READ Accesses
T0
T1
T2
T3
T4
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOP
DOUT
n
DQ
DOUT
a
NOP
DOUT
x
NOP
DOUT
m
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
Note:
Each READ command may be to either bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
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256Mb: x32 Mobile SDRAM
Operation
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 11 on page 26 and
Figure 12 on page 28. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress dataout from the READ. Once the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 (in Figure 13) then the WRITEs at T5 and T7 would be valid, while the WRITE at T6
would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 12
shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 13 shows the case where the additional NOP is
needed.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a fullpage burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS latency minus one. This is shown
in Figure 13 on page 28 for each possible CAS latency; data element n + 3 is either the last
of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note
that part of the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page
bursts.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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256Mb: x32 Mobile SDRAM
Operation
Figure 12: READ to WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
BANK,
COL b
tCK
tHZ
DOUT n
DQ
DIN b
tDS
DON’T CARE
Note:
CL = 3. The READ command may be to any bank, and the WRITE command may be to any
bank. If a burst of one is used, then DQM is not required.
Figure 13: READ to WRITE with Extra Clock Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
DOUT n
DQ
DIN b
tDS
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
CL = 3. The READ command may be to any bank, and the WRITE command may be to any
bank.
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256Mb: x32 Mobile SDRAM
Operation
Figure 14: READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 0 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
BANK a,
ROW
DOUT
n+3
CL = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CL = 3
DON’T CARE
Note:
DQM is LOW.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should
be issued x cycles before the clock edge at which the last desired data element is valid,
where x equals the CAS latency minus one. This is shown in Figure 15 for each possible
CAS latency; data element n + 3 is the last desired data element of a longer burst.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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256Mb: x32 Mobile SDRAM
Operation
Figure 15: Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 0 cycles
ADDRESS
BANK,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CL = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
DQM is LOW.
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256Mb: x32 Mobile SDRAM
Operation
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 15 on page 30.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data
will be ignored (see Figure 17). A full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Figure 16: WRITE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0–A8
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, 1
BANK
ADDRESS
VALID ADDRESS
DON’T CARE
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 17 on page 32. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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256Mb: x32 Mobile SDRAM
Operation
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a
different bank.
Figure 17: WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DIN
n+1
DIN
n
DQ
DON’T CARE
Note:
BL = 2. DQM is LOW.
Figure 18: WRITE to WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
DIN
b
DON’T CARE
Note:
DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 19 on page 33. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated),
and a full-page WRITE burst may be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless of frequency.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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256Mb: x32 Mobile SDRAM
Operation
In addition, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 21. Data n + 1 is either the last of a
burst of two or the last desired of a longer burst. Following the PRECHARGE command,
a subsequent command to the same bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page
bursts.
Figure 19: Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
CLK
DQ
DON’T CARE
Note:
Each WRITE command may be to any bank. DQM is LOW.
Figure 20: WRITE to READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT
b
DOUT
b+1
CLK
DQ
BANK,
COL b
DIN
n
DIN
n+1
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
The WRITE command may be to any bank, and the READ command may be to any bank.
DQM is LOW. CL = 2 for illustration.
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256Mb: x32 Mobile SDRAM
Operation
Figure 21: WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR@ tCK ≥ 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
tWR@ tCK < 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
BANK
(a or all)
BANK a,
COL n
NOP
NOP
ACTIVE
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
DON’T CARE
Note:
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 22, where data n is the last
desired data element of a longer burst.
PRECHARGE
The PRECHARGE command (see Figure 23) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent
row access some specified time (tRP) after the precharge command is issued. Input A10
determines whether one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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256Mb: x32 Mobile SDRAM
Operation
POWER-DOWN
Power-down occurs if CKE is registered low coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no REFRESH operations are performed in
this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 24.
DEEP POWER-DOWN
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained once deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power down.
Figure 22: Terminating a WRITE Burst
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
CLK
DQ
NEXT
COMMAND
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
DQMs are LOW.
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256Mb: x32 Mobile SDRAM
Operation
Figure 23: PRECHARGE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11
All Banks
A10
Bank Selected
BANK
ADDRESS
BA0,1
VALID ADDRESS
DON’T CARE
Figure 24: Power-Down
((
))
((
))
CLK
tCKS
CKE
> tCKS
((
))
COMMAND
((
))
((
))
NOP
NOP
All banks idle
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
ACTIVE
tRCD
tRAS
tRC
DON’T CARE
In order to exit deep power-down mode, CKE must be asserted high. After exiting, the
following sequence is needed in order to enter a new command:
1. Maintain NOP input conditions for a minimum of 100us.
2. Issue PRECHARGE commands for all banks.
3. Issue two or more AUTO REFRESH commands.
The values of the MODE REGISTER and EXTENDED MODE REGISTER will be retained
upon exit deep power down.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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256Mb: x32 Mobile SDRAM
Operation
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 25 and Figure 26.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
Concurrent Auto Precharge
An access command (READ or WRITE) to a second bank while an access command with
auto precharge enabled on a first bank is executing is not allowed by SDRAMs, unless
the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent
auto precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The precharge to bank n will begin when
the READ to bank m is registered (Figure 27).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 28).
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256Mb SDRAM x32_2.fm - Rev. G 6/05
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©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32 Mobile SDRAM
Operation
Figure 25: Clock Suspend During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DIN
n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
BANK,
COL n
ADDRESS
DIN
n
DIN
DON’T CARE
Note:
For this example, BL = 4 or greater, and DM is LOW.
Figure 26: Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
DOUT
n
DQ
NOP
DOUT
n+1
NOP
DOUT
n+2
NOP
DOUT
n+3
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
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256Mb: x32 Mobile SDRAM
Operation
Figure 27: READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
Page Active
READ - AP
BANK n
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
Idle
Interrupt Burst, Precharge
tRP - BANK m
t RP - BANK n
Page Active
BANK m
Precharge
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CL = 3 (bank n)
CL = 3 (bank m)
DON’T CARE
Note:
DQM is LOW.
Figure 28: READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CL = 3 (bank n)
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
DQM is HIGH at T2 to prevent DOUT-a +1 from contending with DIN-d at T4.
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256Mb: x32 Mobile SDRAM
Operation
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency
later. The precharge to bank n will begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 29).
4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 30).
Figure 29: WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
DIN
a
DQ
NOP
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back
Page Active
BANK m
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CL = 3 (bank m)
DON’T CARE
Note:
DQM is LOW.
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
Interrupt Burst, Write-Back
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
DIN
a
NOP
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
DQM is LOW.
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256Mb: x32 Mobile SDRAM
Truth Tables
Truth Tables
Table 8: Truth Table – CKE
Notes: 1–4
CKEn-1
CKEn
Current State
COMMANDn
ACTIONn
L
L
L
H
H
L
Power-Down
Self Refresh
Clock Suspend
Deep Power-Down
Power-Down
Deep Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
All Banks Idle
Reading or Writing
X
X
X
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
BURST TERMINATE
AUTO REFRESH
VALID
See Truth Table 3
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Maintain Deep Power-Down
Exit Power-Down
Exit Deep Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Deep Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
H
H
Notes
8
5
8
6
7
8
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
for clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR
is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during
tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1.
8. Deep Power-Down is power savings feature of this Mobile SDRAM device. This command is
BURST TERMINATE when CKE is HIGH and DEEP POWER DOWN when CKE is LOW.
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Truth Tables
Table 9: Truth Table – Current State Bank n, Command To Bank n
Notes: 1–6; notes appear below table
Current State
CS#
Any
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Idle
Row Active
Read (Auto
Precharge
Disabled)
Write (Auto
Precharge
Disabled)
RAS# CAS#
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
H
L
H
H
X
H
H
L
L
H
L
L
H
L
L
H
H
H
L
L
H
H
H
WE# COMMAND (ACTION)
X
H
H
H
L
L
H
L
L
H
L
L
L
L
H
L
L
L
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
DEEP POWER DOWN
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
DEEP POWER-DOWN
Notes
7
7
11
10
10
8
10
10
8
9
9
10
10
8
9
9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should
be issued on any clock edge occurring during these states. Allowable commands to the
other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. Once tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the row active state
Read w/auto precharge enabled: Starts with registration of a READ command with
auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will
be in the idle state.
Write w/auto precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will
be in the idle state.
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Truth Tables
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these
states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is
met. Once tRC is met, the SDRAM will be in the all banks idle state.
Accessing mode register: Starts with registration of a LOAD MODE REGISTER command
and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks
idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP
is met. Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
9. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER DOWN when CKE
is LOW.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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Truth Tables
Table 10: Truth Table – Current State Bank n, Command To Bank m
Notes: 1–6; notes appear below and on next page
Current State
CS#
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
RAS# CAS#
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
WE#
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7, 10
7, 11
9
7, 12
7, 13
9
7, 8, 14
7,8, 15
9
7,8, 16
7,8, 17
9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read w/Auto Precharge Enabled: Starts with registration of a READ command with
auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will
be in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with
auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will
be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
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Truth Tables
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when
its burst has been interrupted by bank m burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure
10 consecutive read bursts).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figures
12 and 13). DQM should be used one clock prior to the WRITE command to prevent bus
contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure
20), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be
data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will interrupt the WRITE on bank n when registered (Figure
18). The last valid WRITE to bank n will be data-in registered one clock prior to the READ
to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE
to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the dataout appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met,
where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will
be data-in registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank
m is registered. The last valid WRITE to bank n will be data registered one clock to the
WRITE to bank m.
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Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 11: Absolute Maximum Ratings
Voltage/Temperature
Voltage on VDD/VDDQ Supply
Relative to VSS (3.3V)
Relative to VSS (2.5V)
Relative to VSS (1.8V)
Voltage on Inputs, NC or I/O Balls
Relative to VSS (3.3V)
Relative to VSS (2.5V)
Relative to VSS (1.8V)
Operating Temperature
TA (Commercial)
TA (Industrial)
Storage Temperature
Plastic
MIN
MAX
Units
-1
-0.5
-0.35
+4.6
+3.6
+2.8
V
V
V
-1
-0.5
-0.35
+4.6
+3.6
+2.8
V
V
V
0°
-40°
+70°
+85°
C
C
-55°
+150°
C
Table 12: DC Electrical Characteristics and Operating Conditions (LC version)
Notes: 1, 5, 6; notes appear on page 54; VDD = +3.3 ±0.3V, VDDQ = +3.3V ±0.3V
Parameter/Condition
Supply Voltage
I/O Supply Voltage
Input High Voltage: Logic 1; All input
Input Low Voltage: Logic 0; All inputs
Output High Voltage: All inputs: Iout = -4mA
Output Low Voltage: All inputs: Iout = 4mA
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
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46
Symbol
MIN
MAX
Units
VDD
VDDQ
VIH
VIL
VOH
VOL
II
3
3
0.8 x VDDQ
-0.3
VDDQ - 0.2
-5
3.6
3.6
VDDQ + 0.3
0.3
0.2
5
V
V
V
V
V
V
µA
IOZ
-5
5
µA
Notes
22
22
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Electrical Specifications
Table 13: DC Electrical Characteristics and Operating Conditions (V version)
Notes: 1, 5, 6; notes appear on page 54; VDD = +2.5 ±0.2V, VDDQ = +2.5V ±0.2V
Parameter/Condition
Supply Voltage
I/O Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Output High Voltage: All inputs: IOUT = -4mA
Output Low Voltage: All inputs: IOUT = 4mA
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
Symbol
MIN
MAX
Units
VDD
VDDQ
VIH
VIL
VOH
VOL
II
2.3
2.3
0.8 x VDDQ
-0.3
0.9 x VDDQ
-1.0
2.7
2.7
VDDQ + 0.3
0.3
0.2
1.0
V
V
V
V
V
V
µA
IOZ
-1.5
1.5
µA
Notes
22
22
Table 14: DC Electrical Characteristics and Operating Conditions (H version)
Notes: 1, 5, 6; notes appear on page 54; VDD = +1.8 ±0.1V, VDDQ = +1.8V ±0.1V
Parameter/Condition
Symbol
Supply Voltage
I/O Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Output High Voltage: All inputs: Iout = -4mA
Output Low Voltage: All inputs: Iout = 4mA
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
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47
VDD
VDDQ
VIH
VIL
VOH
VOL
II
IOZ
MIN
MAX
1.7
1.9
1.7
1.9
0.8 x VDDQ VDDQ + 0.3
-0.3
+0.3
0.9 x VDDQ
–
–
0.2
-1.0
1.0
-1.5
1.5
Units
V
V
V
V
V
V
µA
Notes
22
22
µA
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Electrical Specifications
Table 15: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11; notes appear on page 54
AC Characteristics
-75
Parameter
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold
time
CS#, RAS#, CAS#, WE#, DQM
setup time
Data-in hold time
Data-in setup time
Data-out high-z time
Data-out low-z time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command
period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b
command
Transition time
WRITE recovery time
Symbol
CL = 3
CL = 2
CL = 1
CL = 3
CL = 2
CL = 1
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MAX
MIN
6
7
-
-10
MAX
MIN
Units
Notes
7
8
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
9
9
1
1.5
3
3
7.5
9
1
2.5
1
tCMS
1.5
2.5
2.5
ns
tDH
1
1.5
1
2.5
1
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDS
1
2.5
3
3
8
9
20
1
2.5
1
tHZ
CL = 3
CL = 2
CL = 1
(3)
(2)
tHZ (1)
tLZ
tOH
t
OHN
tRAS
tRC
6
7
1
2.5
1.8
44
67.5
tRCD
19
tHZ
t
tRP
tRRD
tT
tWR
(a)
WR (m)
tXSR
120000
100
100
100
1
2.5
1.8
48
72
64
80
19
15
120000
48
1.2
7
8
22
1
2.5
1.8
50
90
64
0.5
1 CLK
+7ns
15
80
100
100
100
120000
20
80
19
16
0.3
1 CLK
+
7.5ns
15
67
1
2.5
3
3
10
12
25
1
2.5
1
7
8
19
20
REF
tRFC
7
8
19
MAX
AC (3)
AC (2)
t
AC (1)
t
AH
t
AS
t
CH
t
CL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
tCMH
t
t
Exit SELF REFRESH to ACTIVE
command
MIN
t
-8
64
100
20
20
1.2
0.5
1 CLK
+5ns
15
100
1.2
23
23, 31
10
10
10
27
ns
ms
ns
ns
ns
ns
–
7
24
ns
ns
25
20
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Electrical Specifications
Table 16: AC Functional Characteristics
Notes: 5, 6, 7, 8, 9, 11; notes appear on page 54
Parameter
Symbol
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or
REFRESH command
Data-out to high-z from PRECHARGE command
t
CCD
tCKED
t
PED
DQD
tDQM
t
DQZ
tDWD
t
DAL
tDPL
tBDL
t
CDL
tRDL
tMRD
t
CL = 3
CL = 2
CL = 1
tROH(3)
tROH(2)
tROH(1)
-75
-8
-10
Units
1
1
1
0
0
2
0
5
2
1
1
2
2
1
1
1
0
0
2
0
5
2
1
1
2
2
1
1
1
0
0
2
0
5
2
1
1
2
2
t
3
2
-
3
2
1
3
2
1
tCK
CK
tCK
t
CK
CK
tCK
t
CK
tCK
t
CK
tCK
tCK
t
CK
tCK
tCK
t
tCK
tCK
Notes
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
26
17
17
17
Table 17: IDD Specifications and Conditions (LC version)
Notes: 1, 5, 6, 11, 13; notes appear on page 54; VDD = +3.3V ±0.3V, VDDQ = +3.3V ±0.3V
MAX
Parameter/Condition
Operating current: active mode; Burst = 2; READ or
WRITE; tRC = tRC (MIN)
Standby current: power-down mode; All banks idle;
CKE = LOW
Standby current: power-down mode; All banks idle;
CKE = HIGH
Standby current: active mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
Standby current: active mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
Operating current: burst mode; Continuous burst; READ
or WRITE; All banks active, half DQs toggling every cycle
t
RFC = tRFC (MIN)
Auto Refresh Current
t
CKE = HIGH; CS# = HIGH
RFC = 15.625µs
Deep power-down
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Symbol
-75
-8
-10
Units
Notes
IDD1
170
170
145
mA
IDD2P
400
400
400
µA
3, 18, 19,
28
28
IDD2N
30
30
30
mA
28
IDD3N
40
40
40
mA
IDD3P
30
30
30
mA
IDD4
125
125
100
mA
IDD5
IDD6
IZZ
255
2.5
10
255
2.5
10
205
2.5
10
mA
mA
µA
3, 12, 19,
28
3, 12, 19,
28
3, 18, 19,
28
3, 12, 18,
19, 28, 29
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Electrical Specifications
Table 18: IDD Specifications and Conditions (V version)
Notes: 1, 5, 6, 11, 13; notes appear on page 54; VDD = +2.5 ±0.2V, VDDQ = +2.5 ±0.2V
MAX
Parameter/Condition
Operating current: active mode; Burst = 2; READ or
WRITE; tRC = tRC (MIN)
Standby current: power-down mode; All banks idle;
CKE = LOW
Standby current: power-down mode; All banks idle;
CKE = HIGH
Standby current: active mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
Standby current: active mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
Operating current: burst mode; continuous burst; READ
or WRITE; All banks active, half DQs toggling every cycle
tRFC = tRFC (MIN)
Auto Refresh Current
tRFC = 15.625µs
CKE = HIGH; CS# = HIGH
Deep power-down
Symbol
-75
-8
-10
Units
Notes
IDD1
170
170
145
mA
3, 18, 19, 28
IDD2P
400
400
400
µA
28
IDD2N
30
30
30
mA
28
IDD3N
40
40
40
mA
3, 12, 19, 28
IDD3P
30
30
30
mA
3, 12, 19, 28
IDD4
125
125
100
mA
3, 18, 19, 28
IDD5
IDD6
IZZ
255
2.5
10
255
2.5
10
200
2.5
10
mA
mA
µA
3, 12, 18, 19,
28, 29
Table 19: IDD Specifications and Conditions (H version)
Notes: 1, 5, 6, 11, 13; notes appear on page 54; VDD = 1.8 ±0.1V, VDDQ = 1.8V ±0.1V
MAX
Parameter/Condition
Operating current: active mode; Burst = 2; READ or
WRITE; tRC = tRC (MIN)
Standby current: power-down mode; All banks idle;
CKE = LOW
Standby current: power-down mode; All banks idle;
CKE = HIGH
Standby current: active mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress
Standby current: active mode; CKE = LOW; CS# = HIGH;
All banks active; No accesses in progress
Operating current: burst mode; Continuous burst; READ
or WRITE; All banks active, half DQs toggling every cycle
t
Auto Refresh Current
RFC = tRFC (MIN)
t
CKE = HIGH; CS# = HIGH
RFC = 15.625µs
Deep power-down
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256Mb SDRAM x32_2.fm - Rev. G 6/05
Symbol
-75
-8
-10
Units
Notes
IDD1
125
125
100
mA
3, 18, 19, 28
IDD2P
300
300
300
µA
28
IDD2N
20
20
20
mA
28
IDD3N
30
30
30
mA
3, 12, 19, 28
IDD3P
20
20
20
mA
3, 12, 19, 28
IDD4
85
85
65
mA
3, 18, 19, 28
IDD5
IDD6
IZZ
210
2.5
10
210
2.5
10
170
2.5
10
mA
mA
µA
3, 12, 18, 19,
28, 29
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Electrical Specifications
Table 20: IDD7 – Self Refresh Current Options
Notes: 4, 30; notes appear on page 54 and page 55
Temperature Compensated Self
Refresh Parameter/Condition
MAX
Temperature
VDD = 3.3
VDD = 2.5
VDD = 1.8
Units
Notes
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
800
647
503
432
600
513
437
398
500
447
403
382
450
413
387
373
425
397
378
369
800
647
503
432
600
513
437
398
500
447
403
382
450
413
387
373
425
397
378
369
600
480
370
315
450
380
320
290
375
330
295
278
338
305
283
271
319
293
276
268
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
4, 30
Self Refresh Current:
CKE = LOW – 4-bank refresh
Self Refresh Current:
CKE = LOW – 2-bank refresh
Self Refresh Current:
CKE = LOW – 1-bank refresh
Self Refresh Current:
CKE = LOW – Half-bank refresh
Self Refresh Current:
CKE = LOW – Quarter-bank refresh
Currrent (µA)
Figure 31: Typical Self Refresh Current vs. Temperature – 3.3V Part
600
550
500
450
400
350
300
250
200
150
100
50
0
IDD7 – 4-Bank
IDD7 – 2-Bank
IDD7 – 1-Bank
IDD7 – 1/2-Bank
IDD7 – 1/4-Bank
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (C)
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Electrical Specifications
Currrent (µA)
Figure 32: Typical Self Refresh Current vs. Temperature – 2.5V Part
600
550
500
450
400
350
300
250
200
150
100
50
0
IDD7 – 4-Bank
IDD7 – 2-Bank
IDD7 – 1-Bank
IDD7 – 1/2-Bank
IDD7 – 1/4-Bank
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (C)
Figure 33: Typical Self Refresh Current vs. Temperature – 1.8V Part
450
400
Currrent (µA)
350
300
250
IDD7 – 4-Bank
200
IDD7 – 2-Bank
150
IDD7 – 1-Bank
100
IDD7 – 1/2-Bank
50
IDD7 – 1/4-Bank
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (C)
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Electrical Specifications
Table 21: Capacitance
Note: 2; notes appear on page 54
Parameter
Input Capacitance: CLK
Input Capacitance: All other input-only balls
Input/Output Capacitance: DQs
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Symbol
MIN
MAX
Units
Notes
CI1
CI2
CIO
2.5
2.5
4.0
4.5
4.5
6.0
pF
pF
pF
2
2
2
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Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +1.8V, 2.5V or 3.3V; TA = 25°C; ball under test
biased at 0.9V, 1.25V, and 1.4V respectively. f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (-40°C ≤ TA ≤ +85°C for TA on IT parts) is
ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V, 2.5V at 1.25V, or 3.3V at 1.65V with equivalent
load:
1.8V option
2.5/3.3V option
Q
Q
20pF
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
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256Mb SDRAM x32_2.fm - Rev. G 6/05
30pF
Test loads with full DQ driver strength. Performance will vary with actual system DQ
bus capacitive loading, termination, and programmed drive strength.
tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover
point. If the input transition time is longer than tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.
Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
IDD specifications are tested after the device is properly initialized.
Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
Timing actually specified by tWR.
Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
Address transitions average one transition every two clocks.
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Notes
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75,tCK = 8ns for -8, tCK = 10ns for -10, and CL = 3.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for
a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -8
after the first clock delay, after the last WRITE is executed. May not exceed limit set for
precharge mode.
25. Precharge mode only.
26. JEDEC specifies three clocks.
27. Parameter guaranteed by design.
28. For -10, CL = 3 and tCK = 10ns.
29. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
30. Values for IDD7 for 85C are 100 percent tested. Values for 70C, 45C, and 15C are sampled only.
31. tCK (2) MIN is 9.6 ns for -7.5 and -8 speed 1.8V product.
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Timing Diagrams
Timing Diagrams
Figure 34: Initialize and Load Mode Register1,2
T0
T1
T3
T5
CLK
((
))
((
))
CKE
((
))
((
))
COMMAND5
((
))
((
))
DQM 0-3
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
CODE
((
))
((
))
A10
((
))
((
))
((
))
((
))
CODE
((
))
((
))
T7
T9
T19
T29
((
))
((
tCK ) )
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKS tCKH
tCMS tCMH
NOP
PRE
((
))
((
))
((
))
((
))
LMR4
((
))
((
))
LMR4
((
))
((
))
PRE3
((
))
((
))
AR4
((
))
((
))
AR4
((
))
((
))
ACT4
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
CODE
( ( ALL BANKS
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA
((
))
((
))
tAS tAH
BA0, BA1
((
))
((
))
DQ
((
))
ALL BANKS
tAS tAH
tAS
((
))
((
))
High-Z
tAH
BA0 = L,
BA1 = H
tAS
((
))
((
))
BA0 = L,
BA1 = L
tAH
((
))
((
))
((
))
((
))
tRP
tMRD
tMRD
tRP
T = 100µs
Power-up:
VDD and
CLK stable
Load Extended
Mode Register
Load Mode
Register
tRFC
tRFC
DON’T CARE
Notes: 1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD
MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO
REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address.
3. Optional REFRESH command.
4. The load mode register for both MR/EMR and 2 AUTO REFRESH commands can be in any
order. However, all must occur prior to an ACTIVE command.
5. Device timing is -10 with 100 MHz clock.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 35: Power-Down Mode
T0
T1
tCK
CLK
T2
((
))
((
))
tCL
tCKS
tCH
CKE
tCKS
PRECHARGE
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
Tn + 1
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQML, DQMU
((
))
((
))
A0-A9, A11
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
Violating refresh requirements during power-down may result in a loss of data.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 36: Clock Suspend Mode
T0
T1
tCK
CLK
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tCMS tCMH
DQM 0-3
tAS
A0-A9, A11
tAH
COLUMN m 2
tAS
tAH
tAS
tAH
COLUMN e
2
A10
BA0, BA1
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 37: Auto Refresh Mode
T0
CLK
T1
tCK
T2
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
NOP
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS
DQ
To + 1
((
))
((
))
( ( NOP
))
AUTO
REFRESH
NOP
((
))
((
))
DQM 0-3
BA0, BA1
((
))
((
))
tCL
((
))
CKE
COMMAND
Tn + 1
((
))
((
))
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
BANK
((
))
((
))
tAH
BANK(S)
High-Z
tRP
tRFC
Precharge all
active banks
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
tRFC
DON’T CARE
UNDEFINED
Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not
required.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 38: Self Refresh Mode
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
COMMAND
tCKS
tCKH
tCMS
tCMH
PRECHARGE
Tn + 1
((
))
((
))
((
))
((
))
AUTO
REFRESH
((
))
NOP ( (
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ALL BANKS
SINGLE BANK
tAS
BA0, BA1
DQ
To + 2
AUTO
REFRESH
))
DQM 0-3
A10
To + 1
((
))
((
))
((
))
NOP
((
))
((
))
tAH
BANK(S)
High-Z
((
))
((
))
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
Note:
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256Mb SDRAM x32_2.fm - Rev. G 6/05
Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not
required.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 39: READ – Without Auto Precharge1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
PRECHARGE
tCMH
DQM 0-3
tAS
COLUMN m 2
ROW
A0–A9, A11
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
BANK
tAC
tOH
tOH
tOH
DOUT m + 1
DOUT m + 2
DOUT m + 3
tRP
CL
tHZ
tRAS
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 40: Read – With Auto Precharge1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM 0-3
tAS
A0–A9, A11
tAS
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tRP
CL
tHZ
tRAS
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 41: Single Read – Without Auto Precharge1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP3
NOP3
T6
T7
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
PRECHARGE
NOP
ACTIVE
NOP
tCMH
DQM 0-3
tAS
COLUMN m 2
ROW
A0–A9, A11
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tOH
tAC
DQ
tLZ
tRCD
BANK
DOUT m
tHZ
CL
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.
2. A9 and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 42: Single Read – With Auto Precharge1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP3
READ
T6
T7
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
NOP3
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQM 0-3
tAS
A0–A9, A11
tAS
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tOH
tAC
DQ
DOUT m
tRCD
tHZ
CL
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.
2. A9 and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 43: Alternating Bank Read Accesses1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM 0-3
tAS
A0–A9, A11
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
tAC
tOH
tAC
DQ
tLZ
tRCD - bank 0
BANK 3
DOUT m
tAC
tOH
DOUT m + 1
BANK 0
tAC
tOH
DOUT m + 2
tAC
tOH
DOUT m + 3
tRP - bank 0
CL - bank 0
tAC
tOH
DOUT b
tRCD - bank 0
tRAS - bank 0
tRC - bank 0
tRCD - bank 4
tRRD
CL - bank 4
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 44: Read – Full-page Burst1
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAH
NOP
BURST TERM
NOP
NOP
((
))
((
))
ROW
tAS
((
))
((
))
((
))
((
))
COLUMN m 2
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQM 0-3
A10
Tn + 3
((
))
((
))
tCMS
A0-A9, A11
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
Dout m
DQ
DOUT m+1
tLZ
tRCD
CAS Latency
tAC
tOH
tAC ( (
))
tOH
((
))
DOUT m+2
((
))
tAC
tOH
DOUT m-1
tAC
tOH
DOUT m
tOH
DOUT m+1
tHZ
512 locations within same row
Full page completed
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
DON’T CARE
UNDEFINED
Notes: 1. For this example, CL = 2.
2. A9 and A11 = “Don’t Care.”
3. Page left open; no tRP.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 45: Read – DQM Operation1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
NOP
NOP
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM 0-3
tAS
COLUMN m 2
ROW
A0–A9, A11
tAS
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
tOH
tAC
tAC
tOH
tOH
DQ
DOUT m
tLZ
tRCD
tHZ
CL
tLZ
DOUT m + 2
DOUT m + 3
tHZ
DON’T CARE
UNDEFINED
Notes: 1. For this example, CL = 2.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 46: Write – Without Auto Precharge1
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
T7
T8
T9
PRECHARGE
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM 0-3
tAS
A0–A9, A11
tAS
A10
COLUMN m 3
ROW
tAH
ALL BANKs
ROW
ROW
tAS
BA0, BA1
tAH
ROW
tAH
BANK
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
BANK
tDH
DIN m + 3
tWR2
tRP
tRC
DON’T CARE
Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between and the PRECHARGE command, regardless of frequency.
3. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 47: Write – With Auto Precharge1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM 0-3
tAS
A0–A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
tDH
DIN m + 3
tWR2
tRP
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 48: Single Write – Without Auto Precharge1
T0
T1
tCK
CLK
T2
T3
T4
NOP4
NOP4
T5
T6
T7
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
PRECHARGE
NOP
ACTIVE
NOP
tCMH
DQM 0-3
tAS
COLUMN m 3
ROW
A0–A9, A11
tAS
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
tAH
BANK
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRP
tWR2
tRAS
tRC
DON’T CARE
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between and the PRECHARGE command, regardless of frequency.
3. A9 and A11 = “Don’t Care.”
4. PRECHARGE command not allowed else tRAS would be violated.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 49: Single Write – With Auto Precharge1
T0
T1
tCK
CLK
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
ACTIVE
T9
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
NOP3
ACTIVE
NOP3
NOP3
WRITE
tCMS
NOP
NOP
tCMH
DQM 0-3
tAS
COLUMN m 2
ROW
A0–A9, A11
tAS
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
ROW
tAH
BANK
BANK
tDS
DQ
BANK
tDH
DIN m
tRCD
tRAS
tWR
tRP
tRC
DON’T CARE
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between and the PRECHARGE command, regardless of frequency.
3. A9 and A11 = “Don’t Care.”
4. WRITE command not allowed else tRAS would be violated.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 50: Alternating Bank Write Accesses1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
T9
WRITE
NOP
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
tCMH
DQM 0-3
tAS
A0–A9, A11
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
DIN b
tWR - bank 0
tRCD - bank 0
tDH
BANK 0
tDS
tDH
DIN b + 1
tDS
tDH
DIN b + 2
tRP - bank 0
tRAS - bank 0
tRC - bank 0
tDS
tDH
DIN m + 3
tRCD - bank 0
tWR - bank 1
tRCD - bank 1
tRRD
DON’T CARE
Notes: 1. For this example, BL = 4.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Timing Diagrams
Figure 51: Write – Full-page Burst1
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
A0-A9, A11
A10
((
))
((
))
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m 1
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
tAS
Tn + 3
((
))
((
))
DQM 0-3
tAS
Tn + 2
((
))
((
))
CKE
tCMS
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
tDS
DIN m + 1
tDH
DIN m + 2
tRCD
tDS
tDH
DIN m + 3
((
))
((
))
tDS
tDH
DIN m - 1
512 locations within same row
Full-page burst does
not self-terminate. Can
use BURST TERMINATE
command to stop.2, 3
Full page completed
DON’T CARE
Notes: 1.
2.
3.
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A9 and A11 = “Don’t Care.”
WR must be satisfied prior to PRECHARGE command.
Page left open; no tRP.
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
t
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Timing Diagrams
Figure 52: Write – DQM Operation1
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM 0-3
tAS
A0–A9, A11
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
Notes: 1. For this example, BL = 4.
2. A9 and A11 = “Don’t Care.”
See Table 15, Electrical Characteristics and Recommended AC Operating Conditions, on
page 48.
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Package Dimensions
Package Dimensions
Figure 53: 90-Ball VFBGA (8mm x 13mm)
0.65 ±0.05
SEATING PLANE
C
0.10 C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS: Ø0.40
90X Ø0.45 ±0.05
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER IS Ø0.42
SUBSTRATE MATERIAL: PLASTIC LAMINATE
MOLD COMPOUND: EPOXY NOVOLAC
6.40
0.80 TYP
BALL A1 ID
BALL A1 ID
BALL A1
BALL A9
0.80 TYP
11.20 ±0.10
CL
13.00 ±0.10
5.60 ±0.05
6.50 ±0.05
CL
3.20 ±0.05
1.00 MAX
4.00 ±0.05
8.00 ±0.10
Note:
All dimensions are in millimeters.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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